=====Abel=====

==a==Logik-Beschreibungssprache==a==

//Advanced Boolean Expression Lanaguage (ABEL) is a high-level language (HDL) and compilation system owned and maintained by XILINX.//

D:\fh\praktikum\digitaltechnik_4sem\index.pdf

abl2edif: version M1.5.25 -- Xilinx ABEL Software
Copyright (c) 1996 Xilinx Inc. All Right Reserved.


==a==Beispiele==a==

=a=7-Segment-Anzeige=a=

D:\fh\praktikum\digitaltechnik_4sem\v4\XILINX\ABL\ZU_V42

%%(abel)
module Seg7dec
title '7Segment'

declarations

A0 PIN;
A1 PIN;
A2 PIN;
A3 PIN;

SEG0 PIN istype 'reg';
SEG1 PIN istype 'reg';
SEG2 PIN istype 'reg';
SEG3 PIN istype 'reg';
SEG4 PIN istype 'reg';
SEG5 PIN istype 'reg';
SEG6 PIN istype 'reg';

equations

SEG0 = (!A0# A1# A2# A3) & ( A0# A1#!A2# A3) & (!A0#!A1#!A2# A3) & ( A0#!A1# A2#!A3) & (!A0#!A1#!A2#!A3);
SEG1 = ( A0#!A1# A2# A3) & ( A0# A1#!A2#!A3) & ( A0#!A1#!A2#!A3) & (!A0#!A1#!A2#!A3);
SEG2 = (!A0# A1# A2# A3) & (!A0#!A1# A2# A3) & ( A0# A1#!A2# A3) & (!A0# A1#!A2# A3) & (!A0#!A1#!A2# A3) & (!A0# A1# A2#!A3);
SEG3 = ( A0# A1# A2# A3) & (!A0# A1# A2# A3) & (!A0#!A1#!A2# A3) & ( A0# A1#!A2#!A3);
SEG4 = (!A0# A1#!A2# A3) & ( A0#!A1#!A2# A3) & (!A0#!A1# A2#!A3) & ( A0# A1#!A2#!A3) & ( A0#!A1#!A2#!A3) & (!A0#!A1#!A2#!A3);
SEG5 = (!A0# A1# A2# A3) & ( A0#!A1# A2# A3) & (!A0#!A1# A2# A3) & (!A0#!A1#!A2# A3) & (!A0# A1#!A2#!A3);
SEG6 = (!A0# A1# A2# A3) & ( A0# A1#!A2# A3) & (!A0#!A1# A2#!A3) & (!A0# A1#!A2#!A3);

end Seg7dec
%%


=a=Multiplexer=a=

%%(abel)
module V043
Title 'MUX'

declarations


A PIN;
B PIN;
C PIN;

Y PIN istype 'reg';
Z PIN istype 'reg';
V PIN istype 'reg';
S PIN istype 'reg';

aIn = [A,B,C];
aOut = [Y,Z,V,S];


equations

when (!A & !B & !C) then
aOut=[0,0,0,0]
else

when (A & !B & !C) then
aOut=[1,0,0,0]
else

when (A & B & !C) then
aOut=[0,1,0,0]
else

when (A & B & C) then
aOut=[0,0,1,0]
else

aOut=[0,0,0,1]


test_vectors
([A,B,C] -> [Y,Z,V,S])
[0,0,0] -> [0,0,0,0];
[0,0,1] -> [0,0,0,1];
[0,1,0] -> [0,0,0,1];
[0,1,1] -> [0,0,0,1];
[1,0,0] -> [1,0,0,0];
[1,0,1] -> [0,0,0,1];
[1,1,0] -> [0,1,0,0];
[1,1,1] -> [0,0,1,0];



end V043
%%


=a=Monoflop=a=

%%
module monoflop

monoflop device 'p16v8';

CLK pin 1;
LD pin 2;
D0, D1, D2, D3 pin 3, 4, 5, 6;
Q0, Q1, Q2, Q3 pin 16, 17, 18, 19 istype 'reg';

A pin 15 istype 'com';


DDUAL = [D3,D2,D1,D0];
QDUAL = [Q3,Q2,Q1,Q0];

equations
QDUAL.clk = CLK;

when (!LD)
then QDUAL := DDUAL;
else
when (QDUAL >= 1)
then QDUAL := QDUAL - 1;
else QDUAL := 0;

A = Q0 # Q1 # Q2 # Q3;

test_vectors

([CLK, LD, D3, D2, D1, D0, Q3, Q2, Q1, Q0] -> [Q3, Q2, Q1, Q0, A])
[.c., 0 , 0 , 0 , 1 , 1 ,.x.,.x.,.x.,.x.] -> [0 , 0 , 1 , 1 , 1];
[.c., 1 ,.x.,.x.,.x.,.x., 0 , 0 , 1 , 1 ] -> [0 , 0 , 1 , 0 , 1];
[.c., 1 ,.x.,.x.,.x.,.x., 0 , 0 , 1 , 0 ] -> [0 , 0 , 0 , 1 , 1];
[.c., 1 ,.x.,.x.,.x.,.x., 0 , 0 , 0 , 1 ] -> [0 , 0 , 0 , 0 , 0];
[.c., 0 , 0 , 0 , 1 , 1 , 0 , 0 , 0 , 0 ] -> [0 , 0 , 1 , 1 , 1];



end monoflop;
%%


=a=JK-Master-Slave-FF beschrieben in ABEL=a=

{{image url="images/AbelJKa.pmg.png" alt="JK-Master-Slave-FF"}}

{{image url="images/AbelJK.png" alt="JK-Master-Slave-FF mit asynchronen Setzten (PRE) und Löschen (CLR)"}}

%%
module JKFF
Title 'JKFF'
JKFF device 'P16V8';

declarations
c,j,k,pre,clr pin2,3,4,5,6;
Q,Qn pin 12,14 istype 'com';
Sm pin istype 'com';
Rm pin istype 'com';
qf pin istype 'com';
qfn pin istype 'com';
Ss pin istype 'com';
Rs pin istype 'com';

equations
Sm = Qn & j & c;
Rm = Q & k & c;
qf = !Sm & !qfn;
qfn = !Rm & !qf;
Ss = qf & !c;
Rs = qfn & !c;
Q = !clr & !Ss & !Qn;!
Qn = !pre & !Rs & !Q;

end JKFF
%%

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