history "Abel":tnotes

Revision history for Abel

Revision [7708]

Last edited on 2009-02-01 21:02:16 by ToBo

Additions:

{{image url="images/AbelJK.png" alt="JK-Master-Slave-FF mit asynchronen Setzten (PRE) und Löschen (CLR)"}}

Deletions:

{{image url="images/AbelJK.png" alt="JK-Master-Slave-FF mit asynchronen Setzten (PRE) und Löschen (CLR)
"}}

Revision [7703]

Edited on 2009-02-01 19:26:42 by ToBo

Additions:

{{image url="images/AbelJKa.pmg.png" alt="JK-Master-Slave-FF"}}
{{image url="images/AbelJK.png" alt="JK-Master-Slave-FF mit asynchronen Setzten (PRE) und Löschen (CLR)
"}}

Deletions:

~~{{image url="images/AbelJK.png"}}~~

Revision [7702]

Edited on 2009-02-01 19:22:58 by ToBo

Additions:

==a==Logik-Beschreibungssprache==a==
==a==Beispiele==a==
=a=7-Segment-Anzeige=a=
=a=Multiplexer=a=
=a=Monoflop=a=
=a=JK-Master-Slave-FF beschrieben in ABEL=a=
{{image url="images/AbelJK.png"}}
module JKFF
Title 'JKFF'
JKFF device 'P16V8';
c,j,k,pre,clr pin2,3,4,5,6;
Q,Qn pin 12,14 istype 'com';
Sm pin istype 'com';
Rm pin istype 'com';
qf pin istype 'com';
qfn pin istype 'com';
Ss pin istype 'com';
Rs pin istype 'com';
Sm = Qn & j & c;
Rm = Q & k & c;
qf = !Sm & !qfn;
qfn = !Rm & !qf;
Ss = qf & !c;
Rs = qfn & !c;
Q = !clr & !Ss & !Qn;!
Qn = !pre & !Rs & !Q;
end JKFF

Deletions:

7-Segment-Anzeige
Multiplexer
Monoflop

Revision [7701]

Edited on 2009-02-01 19:16:25 by ToBo

Additions:

Monoflop
module monoflop
monoflop device 'p16v8';
CLK pin 1;
LD pin 2;
D0, D1, D2, D3 pin 3, 4, 5, 6;
Q0, Q1, Q2, Q3 pin 16, 17, 18, 19 istype 'reg';
A pin 15 istype 'com';
DDUAL = [D3,D2,D1,D0];
QDUAL = [Q3,Q2,Q1,Q0];
QDUAL.clk = CLK;
when (!LD)
then QDUAL := DDUAL;
else
when (QDUAL >= 1)
then QDUAL := QDUAL - 1;
else QDUAL := 0;
A = Q0 # Q1 # Q2 # Q3;
([CLK, LD, D3, D2, D1, D0, Q3, Q2, Q1, Q0] -> [Q3, Q2, Q1, Q0, A])
[.c., 0 , 0 , 0 , 1 , 1 ,.x.,.x.,.x.,.x.] -> [0 , 0 , 1 , 1 , 1];
[.c., 1 ,.x.,.x.,.x.,.x., 0 , 0 , 1 , 1 ] -> [0 , 0 , 1 , 0 , 1];
[.c., 1 ,.x.,.x.,.x.,.x., 0 , 0 , 1 , 0 ] -> [0 , 0 , 0 , 1 , 1];
[.c., 1 ,.x.,.x.,.x.,.x., 0 , 0 , 0 , 1 ] -> [0 , 0 , 0 , 0 , 0];
[.c., 0 , 0 , 0 , 1 , 1 , 0 , 0 , 0 , 0 ] -> [0 , 0 , 1 , 1 , 1];
end monoflop;

Revision [6734]

Edited on 2008-11-30 05:11:02 by ToBo

Additions:

//Advanced Boolean Expression Lanaguage (ABEL) is a high-level language (HDL) and compilation system owned and maintained by XILINX.//

Revision [6642]

Edited on 2008-11-28 04:20:41 by ToBo

Additions:

D:\fh\praktikum\digitaltechnik_4sem\index.pdf

Revision [6641]

Edited on 2008-11-28 04:17:48 by ToBo

Additions:

abl2edif: version M1.5.25 -- Xilinx ABEL Software
Copyright (c) 1996 Xilinx Inc. All Right Reserved.
7-Segment-Anzeige
D:\fh\praktikum\digitaltechnik_4sem\v4\XILINX\ABL\ZU_V42
module Seg7dec
title '7Segment'
declarations
SEG0 PIN istype 'reg';
SEG1 PIN istype 'reg';
SEG2 PIN istype 'reg';
SEG3 PIN istype 'reg';
SEG4 PIN istype 'reg';
SEG5 PIN istype 'reg';
SEG6 PIN istype 'reg';
equations
end Seg7dec
Multiplexer
module V043
Title 'MUX'
declarations
A PIN;
B PIN;
C PIN;

Y PIN istype 'reg';
Z PIN istype 'reg';
V PIN istype 'reg';
S PIN istype 'reg';
aIn = [A,B,C];
aOut = [Y,Z,V,S];

equations
when (!A & !B & !C) then
aOut=[0,0,0,0]
else

when (A & !B & !C) then
aOut=[1,0,0,0]
else

when (A & B & !C) then
aOut=[0,1,0,0]
else

when (A & B & C) then
aOut=[0,0,1,0]
else

aOut=[0,0,0,1]

test_vectors
([A,B,C] -> [Y,Z,V,S])
[0,0,0] -> [0,0,0,0];
[0,0,1] -> [0,0,0,1];
[0,1,0] -> [0,0,0,1];
[0,1,1] -> [0,0,0,1];
[1,0,0] -> [1,0,0,0];
[1,0,1] -> [0,0,0,1];
[1,1,0] -> [0,1,0,0];
[1,1,1] -> [0,0,1,0];

end V043

Deletions:

module seg7
Title 'seg7'
Declarations
SEG0 PIN istype 'com';
SEG1 PIN istype 'com';
SEG2 PIN istype 'com';
SEG3 PIN istype 'com';
SEG4 PIN istype 'com';
SEG5 PIN istype 'com';
SEG6 PIN istype 'com';
" <<add your declarations here>>
Equations
end seg7

Revision [6640]

Edited on 2008-11-28 04:10:37 by ToBo

Additions:

=====Abel=====
%%(abel)
module seg7
Title 'seg7'
Declarations
A0 PIN;
A1 PIN;
A2 PIN;
A3 PIN;
SEG0 PIN istype 'com';
SEG1 PIN istype 'com';
SEG2 PIN istype 'com';
SEG3 PIN istype 'com';
SEG4 PIN istype 'com';
SEG5 PIN istype 'com';
SEG6 PIN istype 'com';
" <<add your declarations here>>
Equations
SEG0 = (!A0# A1# A2# A3) & ( A0# A1#!A2# A3) & (!A0#!A1#!A2# A3) & ( A0#!A1# A2#!A3) & (!A0#!A1#!A2#!A3);
SEG1 = ( A0#!A1# A2# A3) & ( A0# A1#!A2#!A3) & ( A0#!A1#!A2#!A3) & (!A0#!A1#!A2#!A3);
SEG2 = (!A0# A1# A2# A3) & (!A0#!A1# A2# A3) & ( A0# A1#!A2# A3) & (!A0# A1#!A2# A3) & (!A0#!A1#!A2# A3) & (!A0# A1# A2#!A3);
SEG3 = ( A0# A1# A2# A3) & (!A0# A1# A2# A3) & (!A0#!A1#!A2# A3) & ( A0# A1#!A2#!A3);
SEG4 = (!A0# A1#!A2# A3) & ( A0#!A1#!A2# A3) & (!A0#!A1# A2#!A3) & ( A0# A1#!A2#!A3) & ( A0#!A1#!A2#!A3) & (!A0#!A1#!A2#!A3);
SEG5 = (!A0# A1# A2# A3) & ( A0#!A1# A2# A3) & (!A0#!A1# A2# A3) & (!A0#!A1#!A2# A3) & (!A0# A1#!A2#!A3);
SEG6 = (!A0# A1# A2# A3) & ( A0# A1#!A2# A3) & (!A0#!A1# A2#!A3) & (!A0# A1#!A2#!A3);
end seg7
%%

Deletions:

~~=====Titel=====~~

Revision [6639]

The oldest known version of this page was created on 2008-11-28 04:10:18 by ToBo

tnotes : Abel

Revision history for Abel

Revision [7708]

Additions:

Deletions:

Revision [7703]

Additions:

Deletions:

Revision [7702]

Additions:

Deletions:

Revision [7701]

Additions:

Revision [6734]

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Revision [6642]

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Revision [6641]

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Revision [6640]

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Deletions:

Revision [6639]